
/*
* Copyright (c) Huawei Technologies Co., Ltd. 2021. All rights reserved.
*/
#include "vpc_reg.h"
// different chn vpc reg
const uint32_t REG_VPC_PIPELINE_OUT_SWAP_ADDR[3] = {REG_VPC_PIPELINE_OUT_SWAP, REG_VPC_PIPELINE2_OUT_SWAP,
    REG_VPC_PIPELINE3_OUT_SWAP};
const uint32_t REG_VPC_OUT_444_TO_422_FILTER_ADDR[3] = {REG_VPC_OUT_444_TO_422_FILTER,
    REG_VPC_OUT2_444_TO_422_FILTER, REG_VPC_OUT3_444_TO_422_FILTER};
const uint32_t REG_VPC_OUT_422_TO_420_FILTER_ADDR[3] = {REG_VPC_OUT_422_TO_420_FILTER,
    REG_VPC_OUT2_422_TO_420_FILTER, REG_VPC_OUT3_422_TO_420_FILTER};
const uint32_t REG_VPC_PIPELINE_RESIZE_ILEFT_ADDR[2] = {VPC_RESIZE_ILEFT_ADDR, VPC_RESIZE2_ILEFT_ADDR};
const uint32_t REG_VPC_PIPELINE_RESIZE_IRIGHT_ADDR[2] = {VPC_RESIZE_IRIGHT_ADDR, VPC_RESIZE2_IRIGHT_ADDR};
const uint32_t REG_VPC_PIPELINE_RESIZE_ITOP_ADDR[2] = {VPC_RESIZE_ITOP_ADDR, VPC_RESIZE2_ITOP_ADDR};
const uint32_t REG_VPC_PIPELINE_RESIZE_IBOTTOM_ADDR[2] = {VPC_RESIZE_IBOTTOM_ADDR, VPC_RESIZE2_IBOTTOM_ADDR};
const uint32_t REG_VPC_PIPELINE_RESIZE_OLEFT_ADDR[2] = {VPC_RESIZE_OLEFT_ADDR, VPC_RESIZE2_OLEFT_ADDR};
const uint32_t REG_VPC_PIPELINE_RESIZE_ORIGHT_ADDR[2] = {VPC_RESIZE_ORIGHT_ADDR, VPC_RESIZE2_ORIGHT_ADDR};
const uint32_t REG_VPC_PIPELINE_RESIZE_OTOP_ADDR[2] = {VPC_RESIZE_OTOP_ADDR, VPC_RESIZE2_OTOP_ADDR};
const uint32_t REG_VPC_PIPELINE_RESIZE_OBOTTOM_ADDR[2] = {VPC_RESIZE_OBOTTOM_ADDR, VPC_RESIZE2_OBOTTOM_ADDR};
const uint32_t REG_VPC_PIPELINE_RESIZE_MISC_CTRL_ADDR[2] = {REG_VPC_RESIZE_MISC_CTRL, REG_VPC_RESIZE2_MISC_CTRL};
const uint32_t REG_VPC_PIPELINE_RESIZE_IN_WIDTH_ADDR[2] = {REG_VPC_RESIZE_IN_WIDTH, REG_VPC_RESIZE2_IN_WIDTH};
const uint32_t REG_VPC_PIPELINE_RESIZE_IN_HEIGHT_ADDR[2] = {REG_VPC_RESIZE_IN_HEIGHT, REG_VPC_RESIZE2_IN_HEIGHT};
const uint32_t REG_VPC_PIPELINE_RESIZE_OUT_WIDTH_ADDR[2] = {REG_VPC_RESIZE_OUT_WIDTH, REG_VPC_RESIZE2_OUT_WIDTH};
const uint32_t REG_VPC_PIPELINE_RESIZE_OUT_HEIGHT_ADDR[2] = {REG_VPC_RESIZE_OUT_HEIGHT, REG_VPC_RESIZE2_OUT_HEIGHT};
const uint32_t REG_VPC_PIPELINE_RESIZE_RND_CTRL0_ADDR[2] = {REG_VPC_RESIZE_RND_CTRL0, REG_VPC_RESIZE2_RND_CTRL0};
const uint32_t REG_VPC_PIPELINE_POSTCROP1_1_ADDR[2] = {REG_VPC_PIPELINE_POSTCROP1_1, REG_VPC_PIPELINE_POSTCROP2_1};
const uint32_t REG_VPC_PIPELINE_POSTCROP1_2_ADDR[2] = {REG_VPC_PIPELINE_POSTCROP1_2, REG_VPC_PIPELINE_POSTCROP2_2};
const uint32_t REG_VPC_PIPELINE_POST_PADDING_VALUE_HOR_L_ADDR[2] = {REG_VPC_POST_PADDING_VALUE_HOR_L,
    REG_VPC_POST_PADDING2_VALUE_HOR_L};
const uint32_t REG_VPC_PIPELINE_POST_PADDING_SIZE_0_ADDR[2] = {REG_VPC_POST_PADDING_SIZE_0,
    REG_VPC_POST_PADDING2_SIZE_0};
const uint32_t REG_VPC_PIPELINE_POST_PADDING_SIZE_1_ADDR[2] = {REG_VPC_POST_PADDING_SIZE_1,
    REG_VPC_POST_PADDING2_SIZE_1};
const uint32_t REG_VPC_PIPELINE_POST_PADDING_RESOLUTION_ADDR[2] = {REG_VPC_POST_PADDING_RESOLUTION,
    REG_VPC_POST_PADDING2_RESOLUTION};
const uint32_t REG_VPC_PIPELINE_POST_PADDING_MODE_ADDR[2] = {REG_VPC_POST_PADDING_MODE, REG_VPC_POST_PADDING2_MODE};
const uint32_t REG_VPC_PIPELINE_UVUP_FILTER_ADDR[3] = {REG_VPC_PIPELINE_UVUP_FILTER, REG_VPC_PIPELINE2_UVUP_FILTER,
    REG_VPC_PIPELINE3_UVUP_FILTER};
const uint32_t REG_VPC_PIPELINE_OUT_CSC_ENABLE_ADDR[3] = {REG_VPC_CSC_ENABLE, REG_VPC_OUT2_CSC_ENABLE,
    REG_VPC_OUT3_CSC_ENABLE};
const uint32_t REG_VPC_PIPELINE_OUT_CSC_MODE_ADDR[3] = {REG_VPC_OUTCSC_MODE, REG_VPC_OUT2_CSC_MODE,
    REG_VPC_OUT3_CSC_MODE};
const uint32_t REG_VPC_PIPELINE_OUT_CSC_0_ADDR[3] = {REG_VPC_OUT_CSC_0, REG_VPC_OUT2_CSC_0,
    REG_VPC_OUT3_CSC_0};
const uint32_t REG_VPC_PIPELINE_OUT_CSC_ALPHA_PADDING_ADDR[3] = {REG_VPC_CSC_ALPHA_PADDING,
    REG_VPC_OUT2_CSC_ALPHA_PADDING, REG_VPC_OUT3_CSC_ALPHA_PADDING};

uint32_t VPC_VPRD0_REG[6] = {VPC_VP_RD_CFG_0, VPC_VP_RD_LWG_0, VPC_VP_RD_FHG_0, VPC_VP_RD_AXI_LINE_0,
    VPC_VP_RD_AXI_FS_HIGH_0, VPC_VP_RD_AXI_FS_0};
uint32_t VPC_VPRD1_REG[6] = {VPC_VP_RD_CFG_1, VPC_VP_RD_LWG_1, VPC_VP_RD_FHG_1, VPC_VP_RD_AXI_LINE_1,
    VPC_VP_RD_AXI_FS_HIGH_1, VPC_VP_RD_AXI_FS_1};
uint32_t VPC_VPRD2_REG[6] = {VPC_VP_RD_CFG_2, VPC_VP_RD_LWG_2, VPC_VP_RD_FHG_2, VPC_VP_RD_AXI_LINE_2,
    VPC_VP_RD_AXI_FS_HIGH_2, VPC_VP_RD_AXI_FS_2};
uint32_t VPC_VPRD3_REG[6] = {VPC_VP_RD_CFG_3, VPC_VP_RD_LWG_3, VPC_VP_RD_FHG_3, VPC_VP_RD_AXI_LINE_3,
    VPC_VP_RD_AXI_FS_HIGH_3, VPC_VP_RD_AXI_FS_3};
uint32_t VPC_VPRD4_REG[6] = {VPC_VP_RD_CFG_4, VPC_VP_RD_LWG_4, VPC_VP_RD_FHG_4, VPC_VP_RD_AXI_LINE_4,
    VPC_VP_RD_AXI_FS_HIGH_4, VPC_VP_RD_AXI_FS_4};
uint32_t VPC_VPRD5_REG[6] = {VPC_VP_RD_CFG_5, VPC_VP_RD_LWG_5, VPC_VP_RD_FHG_5, VPC_VP_RD_AXI_LINE_5,
    VPC_VP_RD_AXI_FS_HIGH_5, VPC_VP_RD_AXI_FS_5};
uint32_t VPC_VPRD6_REG[6] = {VPC_VP_RD_CFG_6, VPC_VP_RD_LWG_6, VPC_VP_RD_FHG_6, VPC_VP_RD_AXI_LINE_6,
    VPC_VP_RD_AXI_FS_HIGH_6, VPC_VP_RD_AXI_FS_6};
uint32_t VPC_VPRD7_REG[6] = {VPC_VP_RD_CFG_7, VPC_VP_RD_LWG_7, VPC_VP_RD_FHG_7, VPC_VP_RD_AXI_LINE_7,
    VPC_VP_RD_AXI_FS_HIGH_7, VPC_VP_RD_AXI_FS_7};
uint32_t VPC_VPRD8_REG[6] = {VPC_VP_RD_CFG_8, VPC_VP_RD_LWG_8, VPC_VP_RD_FHG_8, VPC_VP_RD_AXI_LINE_8,
    VPC_VP_RD_AXI_FS_HIGH_8, VPC_VP_RD_AXI_FS_8};
uint32_t VPC_VPRD9_REG[6] = {VPC_VP_RD_CFG_9, VPC_VP_RD_LWG_9, VPC_VP_RD_FHG_9, VPC_VP_RD_AXI_LINE_9,
    VPC_VP_RD_AXI_FS_HIGH_9, VPC_VP_RD_AXI_FS_9};
uint32_t VPC_VPRD10_REG[6] = {VPC_VP_RD_CFG_10, VPC_VP_RD_LWG_10, VPC_VP_RD_FHG_10, VPC_VP_RD_AXI_LINE_10,
    VPC_VP_RD_AXI_FS_HIGH_10, VPC_VP_RD_AXI_FS_10};

uint32_t* VPC_VPRD_REG_MAP[11] = {
    VPC_VPRD0_REG, VPC_VPRD1_REG, VPC_VPRD2_REG, VPC_VPRD3_REG, VPC_VPRD4_REG, VPC_VPRD5_REG, VPC_VPRD6_REG,
    VPC_VPRD7_REG, VPC_VPRD8_REG, VPC_VPRD9_REG, VPC_VPRD10_REG,
};

uint32_t VPC_VPWR0_REG[5] = {VPC_VP_WR_CFG_0, VPC_VP_WR_AXI_LINE_0, VPC_VP_WR_LWG_0,
    VPC_VP_WR_AXI_FS_HIGH_0, VPC_VP_WR_AXI_FS_0};
uint32_t VPC_VPWR1_REG[5] = {VPC_VP_WR_CFG_1, VPC_VP_WR_AXI_LINE_1, VPC_VP_WR_LWG_1,
    VPC_VP_WR_AXI_FS_HIGH_1, VPC_VP_WR_AXI_FS_1};
uint32_t VPC_VPWR2_REG[5] = {VPC_VP_WR_CFG_2, VPC_VP_WR_AXI_LINE_2, VPC_VP_WR_LWG_2,
    VPC_VP_WR_AXI_FS_HIGH_2, VPC_VP_WR_AXI_FS_2};
uint32_t VPC_VPWR3_REG[5] = {VPC_VP_WR_CFG_3, VPC_VP_WR_AXI_LINE_3, VPC_VP_WR_LWG_3,
    VPC_VP_WR_AXI_FS_HIGH_3, VPC_VP_WR_AXI_FS_3};
uint32_t VPC_VPWR4_REG[5] = {VPC_VP_WR_CFG_4, VPC_VP_WR_AXI_LINE_4, VPC_VP_WR_LWG_4,
    VPC_VP_WR_AXI_FS_HIGH_4, VPC_VP_WR_AXI_FS_4};
uint32_t VPC_VPWR5_REG[5] = {VPC_VP_WR_CFG_5, VPC_VP_WR_AXI_LINE_5, VPC_VP_WR_LWG_5,
    VPC_VP_WR_AXI_FS_HIGH_5, VPC_VP_WR_AXI_FS_5};
uint32_t VPC_VPWR6_REG[5] = {VPC_VP_WR_CFG_6, VPC_VP_WR_AXI_LINE_6, VPC_VP_WR_LWG_6,
    VPC_VP_WR_AXI_FS_HIGH_6, VPC_VP_WR_AXI_FS_6};
uint32_t VPC_VPWR7_REG[5] = {VPC_VP_WR_CFG_7, VPC_VP_WR_AXI_LINE_7, VPC_VP_WR_LWG_7,
    VPC_VP_WR_AXI_FS_HIGH_7, VPC_VP_WR_AXI_FS_7};
uint32_t VPC_VPWR8_REG[5] = {VPC_VP_WR_CFG_8, VPC_VP_WR_AXI_LINE_8, VPC_VP_WR_LWG_8,
    VPC_VP_WR_AXI_FS_HIGH_8, VPC_VP_WR_AXI_FS_8};
uint32_t VPC_VPWR9_REG[5] = {VPC_VP_WR_CFG_9, VPC_VP_WR_AXI_LINE_9, VPC_VP_WR_LWG_9,
    VPC_VP_WR_AXI_FS_HIGH_9, VPC_VP_WR_AXI_FS_9};
uint32_t VPC_VPWR10_REG[5] = {VPC_VP_WR_CFG_10, VPC_VP_WR_AXI_LINE_10, VPC_VP_WR_LWG_10,
    VPC_VP_WR_AXI_FS_HIGH_10, VPC_VP_WR_AXI_FS_10};
uint32_t VPC_VPWR11_REG[5] = {VPC_VP_WR_CFG_11, VPC_VP_WR_AXI_LINE_11, VPC_VP_WR_LWG_11,
    VPC_VP_WR_AXI_FS_HIGH_11, VPC_VP_WR_AXI_FS_11};
uint32_t VPC_VPWR12_REG[5] = {VPC_VP_WR_CFG_12, VPC_VP_WR_AXI_LINE_12, VPC_VP_WR_LWG_12,
    VPC_VP_WR_AXI_FS_HIGH_12, VPC_VP_WR_AXI_FS_12};
uint32_t VPC_VPWR13_REG[5] = {VPC_VP_WR_CFG_13, VPC_VP_WR_AXI_LINE_13, VPC_VP_WR_LWG_13,
    VPC_VP_WR_AXI_FS_HIGH_13, VPC_VP_WR_AXI_FS_13};
uint32_t VPC_VPWR14_REG[5] = {VPC_VP_WR_CFG_14, VPC_VP_WR_AXI_LINE_14, VPC_VP_WR_LWG_14,
    VPC_VP_WR_AXI_FS_HIGH_14, VPC_VP_WR_AXI_FS_14};
uint32_t VPC_VPWR15_REG[5] = {VPC_VP_WR_CFG_15, VPC_VP_WR_AXI_LINE_15, VPC_VP_WR_LWG_15,
    VPC_VP_WR_AXI_FS_HIGH_15, VPC_VP_WR_AXI_FS_15};

uint32_t* VPC_VPWR_REG_MAP[16] = {
    VPC_VPWR0_REG, VPC_VPWR1_REG, VPC_VPWR2_REG, VPC_VPWR3_REG, VPC_VPWR4_REG, VPC_VPWR5_REG, VPC_VPWR6_REG,
    VPC_VPWR7_REG, VPC_VPWR8_REG, VPC_VPWR9_REG, VPC_VPWR10_REG, VPC_VPWR11_REG, VPC_VPWR12_REG, VPC_VPWR13_REG,
    VPC_VPWR14_REG, VPC_VPWR15_REG,
};

#ifdef DVPP_VCAST
static void for_vcast(void)
{
    return;
}
#endif // #ifdef DVPP_VCAST

